1. Field of the Invention
The present invention relates to a technology for checking a connection between terminals of programmable devices.
2. Description of the Related Art
Recently, a programmable device such as a Field Programmable Gate Array (FPGA) is used for generating a prototype of an Application Specific Integrated Circuit (ASIC) that is an integrated circuit manufactured for a specific purpose. Specifically, because the FPGA is a Large Scale Integration (LSI), of which functions can be modified as appropriate by programming when designing the ASIC, the FPGA is used to generate a board logically equivalent to the ASIC to verify whether the ASIC realizes desired functions.
Generally, a plurality of the FPGAs connected with one another are mounted on the board used as the prototype of the ASIC. If connections between the FPGAs are physically disconnected, it is difficult to accurately verify a logic with the board having a logic equivalent to a logic of the ASIC, even when the logic of the ASIC is accurate. To overcome the drawback, a technology is disclosed in Japanese Patent Application Laid-open No. 2004-151061, in which data (usually called “Read Only Memory (ROM) data” or “BIT data” etc.) of a connection-checking program is written to the FPGA and the connections of the boards are checked before verifying the logic. In the technology disclosed in the Japanese Patent Application Laid-open No. 2004-151061, checking data for checking a connection is transacted between input/output pins of the FPGAs connected to one another, and if it is confirmed that the checking data is accurately input to the FPGA on a receiving side, an absence of a physical defect in the connection between the FPGAs is assured.
However, in the technology described above, although the connections between the FPGAs on the board can be checked, connections between the FPGA and devices externally connected to the board cannot be checked. In other words, although connectors for connecting the board to the external devices are arranged on a periphery of the board on which the FPGAs are mounted, the connectors are exclusively used as external terminals of the ASIC and hardly generates or compares the checking data for checking a connection. Therefore, it is difficult to check the connections between the connectors and the FPGA.
To overcome the drawback, a measuring device, such as an oscilloscope etc, can be externally connected to the board via the connector to check whether a connection is established between the connector and the FPGA by checking whether data is output from the FPGA connected to the connectors. In other words, if it is confirmed that the data is output from the connectors using the measuring device, it is determined that there is little physical defect between the FPGA and the connectors. However, due to high integration, a number of the input/output pins of the FPGA is increasing, increasing the number of the input/output pins connected to the connectors. Thus, it is more difficult to manually check the connections between all the input/output pins using the measuring device.
Furthermore, when using the measuring device, the connections are checked on the assumption that all the pins of the FPGAs, which are connected to the connectors, are output pins that output data. However, the pins of the FPGAs also include input pins that input data into the FPGA from the devices externally connected to the board via the connectors. Thus, it is difficult to check the connections based on actual functions.
Similarly, in the conventional technology, because whether each pin is the input pin or the output pin is not considered even when checking the connections between the FPGAs, it is difficult to check the connection based on the actual functions, when the pins are bi-directional pins that control and switch input/output.